Conventionally, an organic package substrate is used for a wiring board in which a semiconductor integrated circuit element (hereinafter referred to as an “IC chip”) is mounted. The wiring board is comprised of: a core board in which a through-hole conductor is formed along an inner wall of a through-hole that penetrates a plate-like core material in the thickness direction of the core board and a filler is charged into the through-holes; and a wiring laminate portion formed in such a manner that a plurality of conductor layers and a plurality of layer-shaped interlayer insulating materials are alternately laminated on a major plane of the core board, and a plurality of via conductors used for an electrical connection between the conductor layers is embedded in the interlayer insulating materials. For example, see Japanese Patent Application Laid-Open (kokai) No. H11-103171 and Japanese Patent Application Laid-Open (kokai) No. 2005-203764.
In recent years, further advanced features of wiring boards have been in demand, and thus wiring boards with high density wiring and large number of layers have been indispensable. As for via conductors, for example, a stacked via, where a series of filled via is formed in a through-hole of an interlayer insulating material, is formed in the thickness direction of the core board so as to save space in the wiring board and improve wiring density. Further advanced features of the wiring board can be achieved by increasing the number of layers of wiring.
However, since a core material (made of resin material, a filler and an interlayer insulating material or the like) and a wiring (made of metal material and via conductors or the like) are integrated to form a wiring board, a problem results from the internal stress (due to differences in the thermal expansion coefficient of these materials) that is concentrated on the wiring and the via conductors or the like. In particular, this internal stress tends to be concentrated on the stacked via where a series of via conductors is formed in the thickness direction of the core board. Further, when the number of via conductors in series (i.e., the number of layers of the interlayer insulating material) is large, the intensity of the internal stress tends to be great. Therefore, when manufacturing a wiring board in which the number of layers of the interlayer insulating material is larger than that of the conventional wiring board (e.g., three layers), a crack is likely to occur at a connection interface of the via conductors constituting a stacked via, thereby resulting in poor electrical reliability.
The present invention has been accomplished in view of the above problems, and an object of the invention is to provide a wiring board having a favorable electrical reliability and in which a crack is unlikely to occur at a connection interface of via conductors even though the number of via conductors in series, which constitutes the stacked via, becomes larger than that of the conventional wiring board.